Advances in technology have opened up many opportunities for applications that go beyond the traditional ways of doing business. Electronic commerce over the Internet has become widely accepted, requiring many companies to either install one or more servers to host a web site and maintain accessible databases or to contract with data centers to provide such services. In addition to performance, important functional characteristics for these servers include reliability, availability and serviceability.
Normally, conventional server architectures feature both processors and memory coupled to a front-side bus. This conventional server architecture greatly hinders server performance due to a number of factors. For instance, one factor is that the front-side bus is non-scalable. Thus, as more processors and memory have access to the front-side bus, bandwidth constraints associated with that bus adversely effect overall server performance. Multi-node architectures where processors, memory and input/output (I/O) components are distributed across multiple interconnected nodes overcomes the limitations of front-side bus and enables building larger systems with scalable server performance.
Another factor is that any node, namely a primary component interconnected to a group of components (referred to as “constituent components”), may be hot-plugged to allow its addition or removal while the operating system (OS) of the server continues to operate. In order to provide a hot-plug solution, however, the constituent components must be represented and visible to the OS of the server. One option is to represent the constituent components, such as one or more processors and memories for example, separately in accordance with a platform firmware interface such as the Advanced Configuration and Power Interface (ACPI) Specification (Version 2.0) published Jul. 27, 2000. However, for those platforms supporting non-uniform memory access (NUMA) architectures, this separate representation poses a number of disadvantages.
For instance, one disadvantage is that the OS would not able to determine proximity relationships between nodes. In other words, the OS would not be able to determine which processor(s) and which memory are interconnected to the same node and adjacent to each other. Such proximity data, if available, would allow the OS to attempt to allocate memory for a processor from the same node in order to avoid time latency penalties caused by accessing memory that is remotely located from that processor.
Another disadvantage is that, during removal of a hot-plugged node, the OS is unable to simultaneously determine which components were removed with the node. Also, during addition of a hot-plugged node inclusive of a processor and memory, the OS of the server may initialize the processor prior to activation of the memory. Hence, the processor specific memory allocation may be inefficient because remotely located memory would be allocated to the processor before local memory is available. This would adversely impact overall server performance and further complicate removal of hot-plugged nodes.
Also, it is contemplated that processor(s) and memory of a node must be initialized to a known state before the OS is made aware of them. When the node is hot-plugged and separate from the substrate maintaining the Basic Input/Output System (BIOS), the BIOS cannot be used for initialization of the processor(s) and memory. One reason is that when the platform under control of the OS, the OS only allows nodes to initiate non-coherent transactions until recognized by the OS. However, the hot-plugged node need to initiate coherent (memory) transactions to reprogram registers to enable various communication ports and links.